How do invisible switches become a computing machine?

This interactive lesson explores the building blocks of a CPU: transistors, logic gates, registers, the ALU, the control unit, pipelines, caches, buses, instruction sets, modern multicore designs, and security mechanisms. Its ten features support classroom demonstrations, review, and independent learning.

Feature 1: Page navigationFeature 2: Theme switchFeature 3: Search and filterFeature 4: Interactive diagramFeature 5: Expandable explanationsFeature 6: Pipeline animationFeature 7: Cache hit simulationFeature 8: Performance calculatorFeature 9: Knowledge quizFeature 10: Learning progress

Learning progress

Click the “I understand this” buttons on the page to advance your progress.

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1. The CPU at work: Fetch, decode, execute, and write-back

CPU stands for Central Processing Unit. It is not simply a “magic chip,” but a complex system of circuits formed by connecting vast numbers of transistors in carefully defined ways. A modern CPU may contain billions to more than a hundred billion transistors. You can think of each transistor as a tiny electronic switch, using its on and off states to represent binary 1s and 0s. A CPU can run programs because software instructions are ultimately encoded in binary and processed step by step by hardware circuits.

The basic operating cycle has five stages. First, fetch: read the next instruction from memory or cache. Second, decode: translate the instruction into control signals the hardware can use. Third, execute: send data to an arithmetic unit, address generation unit, or branch unit. Fourth, memory access: if the instruction reads or writes memory, access the data through caches and buses. Fifth, write-back: store the result in a register or memory. However complex a program may seem, whether it renders a game, runs AI inference, browses the web, or compiles code, it ultimately depends on this cycle.

At a high level, a CPU resembles the brain of a computer. From an engineering perspective, it is more like an extraordinarily precise factory. Instructions are work orders, registers are temporary workbenches, the ALU is the arithmetic workshop, the control unit is the scheduling system, caches are high-speed warehouses, buses are transport routes, and the clock is the metronome. To improve efficiency, modern CPUs use techniques such as pipelining, out-of-order execution, branch prediction, multilevel caches, multiple cores, and hyper-threading. These allow different instructions, or different parts of the same program, to move forward in parallel instead of executing slowly one at a time.

2. An overview of CPU components

1. Transistors and logic gates

Transistors are the fundamental switches in a CPU. Groups of transistors form logic gates such as AND, OR, NOT, and XOR gates. These gates combine to form adders, comparators, multiplexers, and flip-flops.

2. Register file

Registers are the fastest small storage locations inside a CPU. They hold data being processed, addresses, instruction state, and temporary results. Located closest to the execution units, they can be accessed much faster than main memory.

3. Arithmetic logic unit (ALU)

The ALU performs basic operations such as integer addition and subtraction, bitwise AND, OR, and NOT, shifts, and comparisons. It is essential for executing ordinary integer instructions and is the classic computational core of a CPU.

4. FPU and vector units

The floating-point unit (FPU) handles floating-point numbers, while vector units process multiple data elements at once. Image processing, scientific computing, AI preprocessing, and audio and video encoding often rely on parallel data paths using technologies such as SIMD and AVX.

5. Control unit and decoder

The control unit translates instructions into circuit control signals. It determines where data comes from and where it goes, which execution unit operates, and where results are written back.

6. Multilevel caches

Caches are high-speed storage close to the CPU. L1 is the fastest but smallest, L2 is larger, and L3 is often shared by multiple cores. Their purpose is to reduce the time the CPU spends waiting for main memory.

7. Buses and on-chip interconnects

Buses or on-chip networks connect cores, caches, the memory controller, PCIe controllers, and other modules. Modern multicore CPUs often use ring buses or mesh interconnects.

8. Instruction pipeline

A pipeline divides instruction processing into stages: fetch, decode, execute, memory access, and write-back. Like a factory assembly line, it allows multiple instructions to occupy different stages at the same time.

9. Branch predictor

Programs contain many if statements, loops, and jumps. The branch predictor guesses which path execution will take next. Correct predictions keep the pipeline full; incorrect ones require work to be rolled back, reducing performance.

10. Clock and power management

The clock sets the CPU’s rhythm. A higher frequency means more theoretical cycles per second, but also increases power consumption and heat. Modern CPUs dynamically adjust their frequency, voltage, and core power states.

11. Instruction set architecture (ISA)

The ISA is the contract between software and hardware. Architectures such as x86-64, ARM, and RISC-V define instruction formats, registers, memory models, and exception mechanisms.

12. Privilege levels and security

CPUs support user mode, kernel mode, virtualization extensions, and memory protection. These mechanisms provide isolation for ordinary programs, operating systems, virtual machines, and sensitive data.

3. Interactive CPU diagram

Click a module to learn what it does.

Fetch unit

Decoder

Scheduler

Branch predictor

ALU

FPU / SIMD

Load / Store

L1 Cache

L2 Cache

L3 Cache

Memory controller / PCIe / On-chip interconnect

Click any module to begin exploring.

4. Pipelining: Moving several instructions forward at once

Suppose an instruction passes through five stages: fetch, decode, execute, memory access, and write-back. With fully serial execution, the second instruction cannot begin until the first has completed all five stages, which is inefficient. Pipelining turns these stages into five workstations. When the first instruction reaches decode, the second can already be fetched. When the first reaches execute, the second moves to decode, and the third begins fetch. This does not necessarily reduce the latency of a single instruction, but it greatly increases overall throughput.

Cycle	Instruction 1	Instruction 2	Instruction 3	Instruction 4
1	Fetch
2	Decode	Fetch
3	Execute	Decode	Fetch
4	Memory access	Execute	Decode	Fetch
5	Write-back	Memory access	Execute	Decode

Pipelines also face hazards. Data hazards can force a later instruction to wait for an earlier result. Control hazards arise from branches, where an incorrect prediction wastes work already performed. Structural hazards occur when execution resources are insufficient, such as when two operations compete for the same port. Modern CPUs reduce these problems through forwarding, out-of-order execution, register renaming, branch prediction, and wider execution capacity with more available ports.

5. Cache hierarchy: Why can’t the CPU rely on main memory alone?

A CPU computes much faster than DRAM can supply data. If every addition had to fetch its data from main memory, the core would spend much of its time idle. Caches are small, high-speed stores close to the CPU that use locality to improve hit rates. Temporal locality means recently accessed data is likely to be used again soon. Spatial locality means that after one address is accessed, nearby addresses are likely to be accessed too. Traversing an array is usually cache-friendly, while random access to large data structures is more likely to cause cache misses.

L1

The fastest and smallest cache, usually private to each core and split into instruction and data caches. It holds code currently being executed and the most frequently used data.

L2

Larger than L1 with slightly higher latency, and often private to each core. It provides an important buffer between L1 and L3.

L3

The largest cache level, usually shared by multiple cores. It affects multithreaded applications, game frame rates, compilation, databases, and other workloads.

Cache hit simulator

Enter a sequence of addresses from 0–9 to simulate a simple cache that holds four entries.

6. From transistors to instructions: Layers of abstraction

1. The transistor layer

Transistors control whether electrical current can flow. Digital circuits interpret high and low voltage levels as 1 and 0. A modern CPU’s manufacturing process node, leakage current, capacitance, voltage, and cooling all affect how fast it can run and how much power it consumes.

2. The logic gate layer

AND, OR, NOT, and XOR gates express Boolean logic. Any complex computation can be broken down into combinations of logic gates. Binary addition, for example, uses half adders, full adders, and carry chains.

3. Combinational and sequential logic

The output of combinational logic depends only on its current inputs. Sequential logic stores state, using components such as flip-flops, latches, and registers. A CPU needs both the ability to compute and the ability to remember state.

4. The microarchitecture layer

Microarchitecture describes how a particular CPU implements an ISA. Two CPUs may both run x86-64 programs while having entirely different pipeline depths, cache sizes, execution ports, and branch predictors.

5. The software layer

Compilers translate high-level languages into machine instructions. The operating system schedules threads, manages memory, handles interrupts, and enforces access permissions. Program performance often depends on both how the software is written and how the hardware is organized.

7. Performance is about more than GHz

Many people focus only on clock frequency when buying a CPU, but actual performance also depends on IPC, core count, caches, memory bandwidth, power limits, cooling, instruction set optimizations, and how much the software can run in parallel. A 5 GHz CPU with an older architecture may be slower than a 4 GHz CPU with a newer architecture because the newer design can do more work per cycle. IPC stands for Instructions Per Cycle: the number of instructions completed in each clock cycle. In theory, single-thread performance is approximately frequency × IPC. Real programs are also slowed by cache misses, branch mispredictions, I/O, and other factors.

Simple performance estimator

Frequency (GHz)

Average IPC

Effective core count

8. How CPUs and GPUs divide the work

CPUs excel at complex control flow, tasks requiring low latency, operating system scheduling, compilation, game logic, network protocols, and general-purpose programs. GPUs excel at parallel computation over large amounts of similar data, including graphics rendering, matrix multiplication, deep learning training, and video processing. CPUs have relatively few cores, but each core is complex. GPUs have huge numbers of processing units, but each individual execution unit is simpler. In modern computers, the two usually work together: the CPU organizes work, schedules tasks, and handles serial logic, while the GPU delivers high throughput for large-scale parallel computation.

Aspect	CPU	GPU
Goal	Low latency, versatility, complex logic	High throughput, large-scale parallelism
Core design	A few complex cores, large caches, strong branch handling	Many simple processing units, suited to similar parallel tasks
Typical tasks	System scheduling, browsers, compilation, databases, game logic	Rendering, AI, matrix operations, video encoding, scientific computing

9. Advanced mechanisms in modern CPUs

Modern CPUs use many advanced techniques to get more performance. Out-of-order execution lets later, independent instructions run first instead of waiting for an earlier slow instruction. Register renaming maps the registers visible to a program onto a larger set of physical registers, reducing false dependencies. Speculative execution predicts what will happen and begins work before the outcome is known, improving pipeline utilization. Prefetchers use access patterns to bring data into the cache ahead of time. Hyper-threading exposes a single physical core as multiple logical threads, allowing one thread to use resources left idle while another is waiting.

These mechanisms also add complexity. Speculative execution can introduce side-channel security issues. Hyper-threading may be disabled in some security-sensitive environments. Prefetchers work well for regular access patterns but offer limited help with random access. Out-of-order execution improves performance while increasing chip area, verification difficulty, and power consumption. CPU design therefore involves a series of trade-offs, balancing performance, power, cost, area, compatibility, security, cooling, and manufacturing yield.

Front end:Predicts the program’s path, fetches and decodes instructions, and turns complex instructions into internal micro-operations.

Rename and schedule:Renames registers, analyzes dependencies, and sends ready micro-operations to execution units.

Back end:The ALU, FPU, vector units, and load/store units perform the actual computations and memory access.

Retirement:Commits results in the program’s original order so that exceptions and interrupts appear to occur at precise points in execution.

10. Quick quiz

Putting it together: Three layers of CPU understanding

The first layer is physical and electrical: transistors, logic gates, clocks, voltage, power consumption, and cooling determine the CPU’s physical limits. The second is microarchitecture: pipelines, caches, execution units, branch prediction, and out-of-order execution determine real efficiency within a given instruction set. The third is software and systems: compilers, operating systems, thread scheduling, memory access patterns, and algorithms determine whether a program can fully use the hardware’s capabilities. Understanding a CPU takes more than memorizing “ALU, control unit, and registers.” It means seeing the complete system, from electronic switches to the software ecosystem.

When evaluating a CPU, look beyond core count and clock frequency. Consider its architectural generation, single-thread and multithread performance, cache capacity, memory support, PCIe lanes, power limits, motherboard power delivery, cooling conditions, software parallelism, and your actual workload. Games depend heavily on single-thread performance, cache, and memory latency. Compilation benefits from multiple cores and cache. Servers prioritize stability, energy efficiency, I/O, and memory capacity. For AI, the CPU often handles data preparation and scheduling, while large-scale matrix computations are usually assigned to GPUs or specialized accelerators.